?2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6982 " Rev. 1.0.3
4
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin # Name Description
1
IEA
Output of Current Amplifier. This is the output of the PFC current amplifier. The signal from
this pin is compared with sawtooth and determines the pulsewidth for PFC gate drive.
2
IAC
Input AC Current. For normal operation, this input is used to provide current reference for the
multiplier. The suggested maximum I
AC
is 100礎.
3
ISENSE
Current Sense. The non-inverting input of the PFC current amplifier and the output of
multiplier and PFC I
LIMIT
comparator.
4
VRMS
Line-Voltage Detection. The pin is used for PFC multiplier.
5
RDY
Ready Signal. This pin controls the power-on sequence. Once the FAN6982 is turned on and
the FBPFC voltage exceeds in 2.4V, the RDY pin pulls LOW impedance. If the FBPFC voltage
is lower than 1.15V, the RDY pin pulls HIGH impedance.
6
EN
Enable Range Function. The range function is enabled when EN is connected to V
REF
.
The range function is disabled when EN is connected to GND.
7
RT/CT
Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.
8
SGND
Signal Ground.
9
PGND
Power Ground.
10
OPFC
Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped
under 15V to protect the MOSFET.
11
VDD
Power Supply. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively.
The operating current is lower than 10mA.
12
VREF
Reference Voltage. Buffered output for the internal 7.5V reference.
13
FBPFC
Voltage Feedback Input. The feedback input for PFC voltage loop. The inverting input of PFC
error amplifier. This pin is connected to the PFC output through a divider network.
14
VEA
Output of Voltage Amplifier. The error-amplifier output for PFC voltage feedback loop.
A compensation network is connected between this pin and ground.
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